Integrated circuits (ICs) are typically designed using software tools in which designers can combine known components to produce a model for an actual IC. The software can also predict the operation of the modeled device, and the designer can make corrections based on the simulated operation of the modeled circuitry. However, when the IC design is sent to the foundry that produces the actual prototype IC, unexpected defects may occur due to increasingly complicated processing techniques. Such defects are exacerbated as transistor dimensions decrease and advanced processing techniques are utilized. For example, the use of resolution enhancement techniques such as optical proximity correction, phase shift masks, and double patterning lead to variations in lithography that are difficult to accurately model during the design process. Variations in chemical mechanical planarization due to surface density effects and other issues can also contribute to this problem.
When defects either due to the circuit design itself or to the foundry process are detected, the circuit designer may send the defective IC to a failure analysis team to identify the defect so that the design may be corrected. Some defects can be observed using non-destructive techniques, e.g., electro-optical techniques such as LVP (Laser Voltage Probing), SDL (Soft Defect Localization), and LADA (Laser Assisted Device Alteration), among others.
However, some defects require destructive failure analysis methods in which the IC is milled down to a thin film in order to find the region of interest (ROI) for fault detection. One such technique is transmission electron microscopy (TEM), which is commonly used for fault analysis for the latest process nodes (10 nm to 20 nm). At these advanced process nodes, transmission electron microscopy is the only technique with the resolution to pinpoint physical defects in the analyzed integrated circuit.
To employ TEM, the IC being analyzed is milled into thin samples denoted as “lamellae” (plural). A resulting lamella is then subjected to relatively intense electron bombardment (e.g., in a range of 30 kV to 300 kV with 200 kV being typical). The electrons are imaged after passing through the lamella (hence the use of “transmission” in Transmission Electron Microscopy). The relatively large amounts of power used to excite the electrons in TEM causes the electrons to have relatively short wavelengths. As a result, TEM has much finer resolution than other electron-based microscopy techniques, such as scanning electron microscopy (SEM). The resolution for TEM can thus extend down to the atomic scale, which is very useful for isolating faults in modern process nodes.
Although TEM provides robust resolution, the milling of the lamellae becomes problematic at advanced process nodes. In particular, modern process nodes have moved from the traditional planar transistor architectures to three-dimensional structures such as in a fin-shaped field effect transistor (FinFET). FIG. 1 shows an exemplary FinFET transistor 100. FinFETs differ from planar CMOS (Complementary Metal Oxide Semiconductor) devices in that in a CMOS transistor, a gate controls a channel through only one plane. In such planar processes, the gate may not have good control of the channel, exhibiting leakage currents between the source and drain even when the gate is off. In contrast, in FinFET transistors, the channel is a thin vertical fin 105 with the gate (or “finger”) 110 fully wrapped around three sides of the channel. The channel is thus controlled from three planes, which provides better resistance to leakage as compared to planar architectures. In even more advanced nodes, the fin is processed into a nanowire such that the gate completely surrounds the channel. This results in much better control of a highly depleted channel, and thus lower leakage.
The use of TEM for FinFET fault analysis is limited by the three dimensional nature of FinFETs. For example, a lamella may include a plurality of fins 105. In contrast, a lamella for an older process node (a planar technology such as CMOS) has a more homogenous structure such as a single drain, or a single gate, etc. In contrast, a conventional lamella for a TEM analysis of a FinFET will capture multiple fingers or fins. The initial lamella must be relatively thick as the fault (prior to TEM analysis) cannot be isolated to a single fin or finger (gate) but instead only to a collection of these structures. These multiple structures force the microscopist to continue the milling of the lamella until a single FinFET structure is captured in the lamella. For example, the lamella may be milled down until a single fin 105 or gate 110 is isolated.
Although the resulting thinned lamella is then relatively homogeneous such that it is amenable to a subsequent TEM analysis, the microscopist must make an informed guess as to which structure to isolate. The guess may of course be wrong such that another lamella must be milled. Each milling and TEM imaging process may take several days such that the fault analysis becomes protracted. Or worse yet, the failure may be a one-of-a-kind sample that was lost during the milling for the selection of the wrong feature.
Accordingly, there is a need in the art for improved failure analysis for three dimensional device structures, such as FinFETs.